Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).
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e-mail: psliu@issp.ac.cn and psliu@ntu.edu.cn
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June 2014
Technology Review
Advances in the Fabrication Processes and Applications of Wafer Level Packaging
Peisheng Liu,
e-mail: psliu@issp.ac.cn and psliu@ntu.edu.cn
Peisheng Liu
1
Jiangsu Key Laboratory of ASIC Design,
Nantong University
,Nantong 226019
, China
;Nantong Fujistu Microelectronics Co., Ltd
,Nantong 226006
, China
e-mail: psliu@issp.ac.cn and psliu@ntu.edu.cn
1Corresponding author.
Search for other works by this author on:
Jinlan Wang,
Jinlan Wang
Nantong University
,Nantong 226019
, China
Search for other works by this author on:
Liangyu Tong,
Liangyu Tong
2
Jiangsu Key Laboratory of ASIC Design,
Nantong University
,Nantong 226019
, China
2Present address: Wu Xi Zhong Wei High-Tech Electronics Co., Ltd., Wuxi 214035, China.
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Yujuan Tao
Yujuan Tao
Nantong Fujistu Microelectronics Co., Ltd.
,Nantong 226006
, China
Search for other works by this author on:
Peisheng Liu
Jiangsu Key Laboratory of ASIC Design,
Nantong University
,Nantong 226019
, China
;Nantong Fujistu Microelectronics Co., Ltd
,Nantong 226006
, China
e-mail: psliu@issp.ac.cn and psliu@ntu.edu.cn
Jinlan Wang
Nantong University
,Nantong 226019
, China
Liangyu Tong
Jiangsu Key Laboratory of ASIC Design,
Nantong University
,Nantong 226019
, China
Yujuan Tao
Nantong Fujistu Microelectronics Co., Ltd.
,Nantong 226006
, China
1Corresponding author.
2Present address: Wu Xi Zhong Wei High-Tech Electronics Co., Ltd., Wuxi 214035, China.
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 7, 2014; final manuscript received April 6, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie.
J. Electron. Packag. Jun 2014, 136(2): 024002 (7 pages)
Published Online: April 29, 2014
Article history
Received:
January 7, 2014
Revision Received:
April 6, 2014
Citation
Liu, P., Wang, J., Tong, L., and Tao, Y. (April 29, 2014). "Advances in the Fabrication Processes and Applications of Wafer Level Packaging." ASME. J. Electron. Packag. June 2014; 136(2): 024002. https://doi.org/10.1115/1.4027397
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