Presently, stack dice are used widely as low-power memory applications because thermal management of 3D architecture such as high-power processors inherits many thermal challenges. Inadequate thermal management of three-dimensional integrated circuits (3D-ICs) leads to reduction in performance, reliability, and ultimately system catastrophic failure. Heat dissipation of 3D systems is highly nonuniform and nonunidirectional due to many factors such as power architectures, transistors packing density, and real estate available on the chip. In this study, the development of an experimental model of an active cooling method to cool a 25 W stack-dice to approximately utilizing a multidimensional configured thermoelectric will be presented.
Issue Section:Technical Briefs
Keywords:cooling, integrated circuit packaging, integrated circuit reliability, thermal management (packaging)
J., 2001, “
Enhanced Heat Transfer Using Nanofluids,” U.S. Patent No. 6,221,275.
C., 2005, “
Multi-Stack Flip Chip 3D Packaging With Copper Plated Through-Silicon Vertical Interconnection,”
Electronic Packaging Technology Conference,
New York, pp.
Thermal Management in a 3D-PCB-Package With Water Cooling,
New York, pp.
M., 2003, “
Active Temperature Gradient Reducer,” U.S. Patent No. 6,581,388.
R. E., and
D. T., 1995, “
Thermoelectric Cooling Assembly With Optimized Fin Structure for Improved Thermal Performance and Manufacturability,” U.S. Patent No. 5,456,081.
Copyright © 2010
by American Society of Mechanical Engineers