A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young’s modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias. [S1043-7398(00)01203-2]
Skip Nav Destination
e-mail: h.lu@gre.ac.uk
Article navigation
September 2000
Technical Papers
Reliability Analysis of Flip Chip Designs Via Computer Simulation
Hua Lu,
e-mail: h.lu@gre.ac.uk
Hua Lu
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
Search for other works by this author on:
C. Bailey,
C. Bailey
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
Search for other works by this author on:
M. Cross
M. Cross
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
Search for other works by this author on:
Hua Lu
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
e-mail: h.lu@gre.ac.uk
C. Bailey
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
M. Cross
School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD August 3, 1999; revised manuscript received January 17, 2000. Associate Technical Editor: B. Courtois.
J. Electron. Packag. Sep 2000, 122(3): 214-219 (6 pages)
Published Online: January 17, 2000
Article history
Received:
August 3, 1999
Revised:
January 17, 2000
Citation
Lu, H., Bailey , C., and Cross, M. (January 17, 2000). "Reliability Analysis of Flip Chip Designs Via Computer Simulation ." ASME. J. Electron. Packag. September 2000; 122(3): 214–219. https://doi.org/10.1115/1.1286122
Download citation file:
Get Email Alerts
Anand Model Constants of Sn–Ag–Cu Solders: What Do They Actually Mean?
J. Electron. Packag (June 2025)
Sequential Versus Concurrent Effects in Combined Stress Solder Joint Reliability
J. Electron. Packag (June 2025)
Related Articles
On Failure Mechanisms in Flip Chip Assembly—Part 1: Short-Time Scale Wave Motion
J. Electron. Packag (June,2008)
Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials
J. Electron. Packag (June,2005)
On Failure Mechanisms in Flip Chip Assembly—Part 2: Optimal Underfill and Interconnecting Materials
J. Electron. Packag (June,2008)
Related Proceedings Papers
Related Chapters
Openings
Guidebook for the Design of ASME Section VIII Pressure Vessels, Third Edition
Openings
Guidebook for the Design of ASME Section VIII Pressure Vessels
Piping Design
Power Boilers: A Guide to the Section I of the ASME Boiler and Pressure Vessel Code, Second Edition