The temperature rise in compact silicon devices is predicted at present by solving the heat diffusion equation based on Fourier’s law. The validity of this approach needs to be carefully examined for semiconductor devices in which the region of strongest electronphonon coupling is narrower than the phonon mean free path, Λ, and for devices in which Λ is comparable to or exceeds the dimensions of the device. Previous research estimated the effective phonon mean free path in silicon near room temperature to be near 300 nm, which is already comparable with the minimum feature size of current generation transistors. This work numerically integrates the phonon Boltzmann transport equation (BTE) within a two-dimensional Silicon-on-Insulator (SOI) transistor. The BTE is coupled with the classical heat diffusion equation, which is solved in the silicon dioxide layer beneath a transistor with a channel length of 400 nm. The sub-continuum simulations yield a peak temperature rise that is 159 percent larger than predictions using only the classical heat diffusion equation. This work will facilitate the development of simpler calculation strategies, which are appropriate for commercial device simulators.

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